1. Field of the Invention
This invention relates to analog-to-digital converters (ADCs), and more particularly to exclusive OR (XOR) gates and latch circuits used in flash ADCs.
2. Description of the Related Art
Flash ADCs take their name from their high conversion speed. They employ a precision voltage reference that is divided by a precision resistor divider to provide individual comparator reference voltages. As the input voltage increases the comparators switch in turn, and a decode logic network provides an appropriate digital output as a function of the state of the comparator input voltages. On a typical n-bit flash ADC, 2.sup.n-1 comparators and 2.sup.n-1 corresponding resistor taps must generally be used. An 8-bit converter would require, for example, 255 comparators and 255 resistor taps.
FIG. 1 is a block diagram of a conventional 4-bit ADC. A resistor string consisting of fourteen series resistors R1-R14 is connected between positive and negative voltage reference terminals 2 and 4. Fifteen input preamplifiers A1-A15 are provided, with each preamp inverting input receiving its input from a respective tap off the resistor string. The non-inverting preamp inputs are all connected to an input terminal 6 to receive an analog input signal that is to be converted to digital format. The output of each preamp A1-A15 is connected to a respective latching comparator, L1-L15, with a clock input 8 connected to each of the latching comparators and periodically causing them to latch the output of their respective preamps.
As the analog input signal at terminal 6 swings from its full negative to its full positive excursion, the outputs from each of the preamps toggle from 0 to 1 in turn, beginning with A15 for the most negative and progressing through A1 for the most positive input. The resultant set of digital preamp outputs is referred to as a thermometer code. With this code format, if the output of a given preamp is a logic 1, then the outputs from all of the preamps of lower bit order (vertically below the on preamp in FIG. 1) are also logic 1s.
Contingent upon the presence of a thermometer code format, the ADC's decoding logic can be greatly simplified by using a "gray-code" decoding scheme. This type of decoding logic uses XOR gates whose operation is based upon current summations. For the 4-bit ADC of FIG. 1, 7 XOR gates XOR1-XOR7 are interconnected with each other in a known fashion to produce a 4-bit digital output that is captured by four corresponding output latches L16-L19. The first rank of four XOR gates XOR1-XOR4 are current mode (CM) devices that receive thermometer code inputs from respective sets of latches L1-L15. The second and third ranks, consisting respectively of XOR5, XOR6 and of XOR7, are voltage mode (VM) devices that receive inputs from the preceding rank; their inputs do not have to be in a thermometer code format. Operating under the control of the clock input 8, the output latches yield the 4-bit digital output designated as bits B1-B4.
A limiting amplifier buffer BFR1 converts the sine wave clock signal to a square wave suitable for controlling the digital circuitry. Three more buffers BFR2, BFR3 and BFR4 in series with BFR1 provide gate delays to synchronize the clock signal at the output latches L16-L19 with the logic signals that propagate through three ranks of XOR gates. Additional buffers BFR5-BFR10 provide gate delays for connections between the decode network and the output latches that bypass one of more ranks of XOR gates.
FIG. 2 shows a current mode XOR gate that has been used in the decoding section of the FIG. 1 ADC. The gate is illustrated as having either three or five inputs. It includes a pair of resistors R15, R16 that are connected between a positive voltage bus Vcc (typically +5 volts) and the current (collector-emitter) circuits of a pair of matched npn bipolar transistors Q1, Q2. Both transistors are biased into conduction by a common bias signal Vb. The gate outputs Y and Y, corresponding to logic 1 and logic 0 outputs, are taken respectively from the R15/Q1 and the R16/Q2 junctions.
The gate inputs are supplied by respective differential transistor pairs, each of which correspond to a respective preamplifier of FIG. 1. For a three input device, in which the inputs are designated A, B and C, the most significant bit (MSB) input consists of differentially connected bipolar transistors Q3, Q4 that are biased respectively by input A and the complement of A (A). Their emitters are connected in common to a current source I1, while their collectors are connected to draw current from the current circuits of Q2 and Q1, respectively. The other input differential pairs have similar designs. The second MSB input comprises transistors Q5, Q6 and another I1 current source, while the least significant bit (LSB) input consists of differentially connected transistors Q7, Q8 and another current source I1. The inputs B and C are applied to the bases of Q5 and Q7, with complementary input signals B and C applied to the bases of Q6 and Q8, respectively. The insertion of Q1 and Q2 between R15, R16 and differential pairs Q3-Q8 allows for a higher speed operation than would be the case if the resistors were connected directly to Q3-Q8.
The connections of the differential input pairs to the transistors Q1, Q2 alternates from pair to pair. That is, whereas the differential transistors for A and A (Q3 and Q4) are connected respectively to the collectors of Q2 and Q1, the differential transistors for B and B (Q5 and Q6) are connected respectively to the collectors of Q1 and Q2, and the third differential transistor pair again alternates so that the input transistors for C and C (Q7 and Q8) are connected respectively to the collectors of Q2 and Q1, the same as for the MSB input pair.
The response of the 3-input XOR to thermometer code inputs is illustrated in the truth table of FIG. 3a. First assume that the inputs A, B and C are all at a logic 0 level (with the complementary inputs A, B and C at a logic 1 level). This is indicated on line 1 of FIG. 3a. With this input pattern, the transistors Q3, Q5 and Q7 are held OFF, while transistors Q4, Q6 and Q8 are ON. Thus, two units of current (2I1) flow through R15, and one unit of current (I1) flows through R16. With R15 and R16 having equal resistance values, this produces a voltage drop across R15 that is twice the voltage drop across R16. Subtracting these voltage drops from Vcc yields a higher voltage for output Y than for output Y; the output Y is accordingly a logic zero and its complement Y is a logic one.
If the LSB input C now goes high, as indicated on line 2 of FIG. 3a, transistor Q7 turns ON and Q8 turns OFF, and one unit of current is shifted from R15 to R16. This results in a lower voltage drop across R15 than R16, and consequently a logic 1 Y output.
The next higher input pattern, illustrated on line 3, is for input B to be high and the other inputs A and C low. However, such an input pattern violates the thermometer code pattern and accordingly no outputs from the XOR gate are given, as indicated by dashes through the I.sub.R15, I.sub.R16, Y and Y columns for this nonallowable state. The next higher input pattern, with B and C high and A low, is consistent with the thermometer code. As illustrated on line 4, this input pattern shifts one unit of current from R16 back to R15 (because of Q5 turning ON and Q6 OFF). The result is that output Y is a logic 0, while the complementary output Y is a logic 1.
The next three input patterns in progressively higher binary order, shown on lines 5-7, all violate the thermometer code pattern. The final possible input pattern, shown on line 8, is for all three inputs A, B and C to be logic 1. In this event one unit of current is shifted from R15 to R16 (compared to the line 4 pattern), with the Y output a logic 1 and the complementary Y output a logic 0.
It can be seen from an inspection of FIG. 3a that, for a gray-code input, the Y output is a logic 1 when an odd number of inputs are high, and a logic 0 when an even number of inputs are high. This satisfies the basic definition of the XOR function.
FIG. 3b presents a truth table for a five input XOR gate. In this case new differential transistor pairs Q9, Q10 and Q11, Q12, of lower bit significance than the other transistor pairs and with respective base inputs D, D and E, E, have been added to the three input case. Continuing the alternating pattern of connections, Q9 and Q10 are connected to draw current from R15 and R16, while the collectors of Q11 and Q12 are connected to draw current from R16 and R15, respectively. Three units of current (3I1) are drawn through R15 and two units (2I1) through R16 for thermometer code input patterns in which an even number of inputs are high, while two units of current are drawn through R15 and three units through R16 for thermometer code input patterns in which an odd number of inputs are high. This again satisfies the basic XOR function.
A thermometer code XOR gate requires an odd number of inputs in addition to the gray-code. If an even number of inputs is desired, the gate is implemented with the next higher odd number of inputs, and one of the inputs is forced to a constant logic 0 state. This is illustrated in FIG. 2 by replacing the Q11, Q12 transistor pair with a current source I1 that is connected directly between the R15/Q1 circuit and ground, as indicated by dashed line 9. An equivalent truth table for this gate with four effective inputs can be obtained from FIG. 3b by considering only those lines in the table for which column E is a logic 0 and the remaining columns A-D follow a thermometer code pattern.
ADCs of the type illustrated in FIG. 1 have a fairly high level of complexity and are not well adapted to the continual need for greater resolution (i.e., more bits) and higher conversion rates. To increase the operating range, the same number of circuit elements have to work at higher and higher speeds. For resolutions above 8 or 10 bits, more than one monolithic integrated circuit is usually required, and both cost and power consumption are relatively high.
Other types of ADCs have been explored in recent years, in particular folding/interpolation devices in which a certain degree of ADC decoding is performed on the analog signal prior to its being latched. Input currents are summed together and differential voltages are produced across resistor pairs, with the voltages latched by standard latching comparators. A performance limitation of the folding/interpolation approach is that each amplifier's output changes polarity multiple times as the input signal goes from its lowest to its higher value. This effectively increases the amplifier's output frequency. Since such amplifiers are limited in bandwidth, the output signal amplitude falls off at higher frequencies and their analog input bandwidth suffers compared to conventional flash ADCs. Folding/interpolation devices are disclosed, for example, in Corcoran et al., "A 400 MHz 6b ADC", IEEE International Solid-State Circuit Conference, Feb. 24, 1984, pages 294-296; van de Grift et al., "An 8b 50 MHz Video ADC with Folding and Interpolation Techniques", IEEE International Solid-State Circuits Conference, 1987, pages 94, 95, 354; and Van de Plassche, "An 8-bit 100-MHz Full Nyquist Analog-to-Digital Converter", IEEE Journal of Solid State Circuits, Vol. 23, No. 6, December 1988, pages 1334-1344.